VHDL - Digital system modeling and Verification

Who may attend the course?

Engineering Students (Comp. Sc, Electrical, Electronics, Instrumentation and others)

Teachers & Industry participants interested in VLSI Systems design

Budding Researchers and Technology enthusiasts

And others who want to build a career in  High Level Design in VLSI or want to pursue higher studies (MS) in the related field and fulfill the following prerequisites of the coursework.

Prerequisites:

Understanding of Binary Arithmetic

Digital logic and simple digital circuits

Basic programming knowledge

Experience in Linux environment is a Plus

Strong motivation to learn a new technology is a must

Creativity in thinking and problem solving is essential

Proficiency in English is desired.

Objective:

VHDL is one of the most popular Hardware Description Languages used in the Industry for Hardware modeling of Digital Systems. Hardware modeling is the first and most important step in building a modern digital VLSI system. A synthesizable and functionally verified model of the system can significantly reduce the design time and development complexity of the VLSI system before it is sent out to Fab-lab for Fabrication.

In this course we'll learn how to model digital systems , VHDL language constructs and system modeling techniques with VHDL. It is important to verify that the model we have generated is correct and conform with the system specification. There are various design verification techniques with varying degree of effectiveness and runtime efficiency. However the design community is still relying on the time tested method of writing Testbenches and running simulation to verify their design. In this course we'll also learn how to write Testbenches and how to verify your design by running simulation.

Course Outline:

Refresher:    Binary Arithmetic, Boolean logic

   Digital Logic and Digital circuits

Motivation:  Actual implementation of a simple Digital Hardware model in VHDL and simulate the model for functional verification (by the Instructor)

Fundamental concepts of VHDL

Modeling Digital systems

VHDL Modeling Concepts

VHDL as a programming language

Lexical Elements and Syntax

Constants and Variables

Scalar Types

Sequential Statements

Array Types and Operations

Basic Modeling Constructs

Entity – Architecture

Behavioral Description

Structural Description

Subprograms

Procedures and Functions

Packages and use Clause

Package declaration and Bodies

Use Clause

Resolved Signals

IEEE Std_Logic_1164 Resolved Siganals

Resolved Signals and Ports

Generic Constants

Parameterizing Behavior

Parameterizing Structure

Model simulation

Writing Testbench

Digital Hardware Simulation concepts

Functional verification with VHDL simulation

Final Project:

Design Platform:

Xilinx ISE developement environment and Modelsim simulator from MentorGraphics for Hardware Model Simulation and verification.

Faculty:      Abhijit Das

Course fees & Timing:

The regular course work has a duration of 4 weeks and the course fee is set to INR 8000/-.  However, there are Discount options ...  for eligible candidates.

See Class Timing for details of timing patterns of lecture classes and project assignments.

Course Previews: A quick sneak peak of our Learning Management System

How to start the Admission process:

Register for the Aptitude Test, or

Contact us for more information to get started